1. Field of the Invention
The invention lies in the integrated technology field. More specifically, the invention relates to an integrated circuit which generates a phase-shifted output clock signal from a first clock signal. The phase shift is thereby adjustable.
One way of obtaining an adjustable phase shift of an output clock signal relative to an input clock signal consists in providing a series circuit formed by a plurality of identical delay elements, to which the input clock signal is fed on the input side. All of the delay elements thereby have the same delay time. The output signals of the series-connected delay elements have a respectively different phase shift relative to the input clock signal, since the delay time of the delay elements is short relative to the clock period of the input clock signal. The output signal of an arbitrary one of the delay elements can be selected by a multiplexer, by means of a control signal. Consequently, by driving the multiplexer, an output clock signal having the desired phase shift relative to the input clock signal can be taken from the series circuit of delay elements.
Inverters, for example, are used as delay elements. However, their minimum delay time is dependent on the production technology that is employed and cannot, therefore, be shortened arbitrarily. It follows from this that the phase shift of the output clock signal relative to the input clock signal can be altered only in relatively coarse steps corresponding to the delay time of the individual delay elements.
2. Summary of the Invention
The object of the invention is to provide an integrated circuit for generating from a clock signal a phase shifted output clock signal which overcomes the above-noted deficiencies and disadvantages of the prior art devices and methods of this kind, and which allows the phase shift between the first clock signal and the output clock signal to be adjusted and altered in finer steps.
With the above and other objects in view there is provided, in accordance with the invention, an integrated circuit, comprising:
an adjustable current source having a first output outputting a first adjustable current and a second output outputting a second adjustable current, wherein a sum of the first and second currents is substantially constant for different settings, and at least one control input for receiving a control signal for setting the first and second currents;
a first transistor connected between the first output of the current source and a supply line for a first potential, the first transistor having a first channel terminal connected to the supply line and a second channel terminal remote therefrom, and a second transistor connected between the second output of the current source and the supply line for the first potential, the second transistor having a first channel terminal connected to the supply line and a second channel terminal remote therefrom;
a circuit node and a precharge unit connected to the circuit node for precharging the circuit node to a second potential;
a series circuit formed by a third transistor and a fourth transistor connected between the circuit node and the supply line;
the third transistor having a control terminal connected to a first clock signal, the first transistor having a control terminal connected to the second channel terminal thereof, and
the fourth transistor having a control terminal connected to the control terminal of the first transistor;
a series circuit formed by a fifth transistor and a sixth transistor connected between the circuit node and the supply line;
the fifth transistor having a control terminal connected to a second clock signal, phase-shifted relative to the first clock signal, the second transistor having a control terminal connected to the second channel terminal thereof, and the sixth transistor having a control terminal connected to the control terminal of the second transistor; and
a level detector having an input connected to the circuit node and an output supplying an output clock signal at a first level if the potential at the circuit node lies below a lower switching threshold of the level detector, and at a second level if the potential at the circuit node lies above an upper switching threshold.
In accordance with the invention, therefore, the phase shift between the output clock signal and the first clock signal is set by altering the values of the two currents supplied by the current source. The finer the adjustment steps for the two currents, the finer the steps in which the phase shift can be altered. In this case, the step size of the adjustable phase shift is dependent on the "resolution" of the adjustable current source and no longer on the production technology of the integrated circuit.
In accordance with an added feature of the invention, the integrated circuit further comprises:
an adjustable delay unit having an input receiving an input clock signal, an output for the first clock signal, and a control input for setting a delay time thereof;
a phase comparator having a first input connected to the input clock signal, a second input connected to the output of the level detector, and an output; and
a phase regulator having an input connected to the output of the phase comparator, the phase regulator generating a coarse control signal and a fine control signal depending on a phase difference ascertained by the phase comparator, and having a first output for outputting the coarse control signal connected to the control input of the delay unit and a second output for outputting the fine control signal connected to the control input of the adjustable current source.
In accordance with an additional feature of the invention, the phase shift between the first clock signal and the second clock signal is substantially equal to a minimum delay step of the delay unit by which a delay time of the delay unit is adjustable with the coarse control signal.
In accordance with another feature of the invention, the delay unit comprises a series circuit of delay elements each having a delay time corresponding to the minimum delay step; and the first clock signal generated by the delay unit is an input signal of a given one of the delay elements and the second clock signal is an output signal of the given delay element.
In accordance with a further feature of the invention, the first clock signal generated by the delay unit is an output signal of one of the delay elements; and the circuit has an additional delay element, having a delay time substantially corresponding to the delay time of the delay elements of the delay unit, having an input connected to the output of the delay unit, and having an output supplying the second clock signal.
In accordance with again a further feature of the invention, a first capacitor is connected between the supply line and the control terminals of the first and fourth transistors, and a second capacitor is connected between the supply line and the control terminals of the second and sixth transistors.
In accordance with a concomitant feature of the invention, the first output of the current source is connected to the supply line via a series circuit formed by the first transistor and a seventh transistor; the second output of the current source is connected to the supply line via a series circuit formed by the second transistor and an eighth transistor; and the seventh transistor and the eighth transistor each has a control input connected to a supply line for the second potential.
Other features which are considered as characteristic for the invention are set forth in the appended claims.
Although the invention is illustrated and described herein as embodied in an integrated circuit for generating a phase-shifted output clock signal from a clock signal, it is nevertheless not intended to be limited to the details shown, since various modifications and structural changes may be made therein without departing from the spirit of the invention and within the scope and range of equivalents of the claims.